Computer architectures are moving from interfacing discrete components on a printed circuit board or through use of other package configurations, to integrating multiple components onto a single integrated chip, which is commonly referred to as a System on a Chip (SoC) architecture. SoCs offer a number of advantages, including denser packaging, higher speed communication between functional components, and lower temperature operation. SoC designs also provide standardization, scalability, modularization, and reusability.
While SoC architectures are the wave of the future, the present some challenges with respect to verification of design and integration when compared with using discrete components. For example, for many years personal computers employed INTEL's ubiquitous “North” bridge and “South” bridge architecture, wherein a central processing unit was interfaced to a memory controller hub (MCH) chip via a first set of buses, and the memory controller hub, in turn, was interfaced to an Input/Output controller hub (ICH) chip via another set of buses. Each of the MCH and ICH further provided interface to various system components and peripherals via further buses and interfaces. Each of these buses and interfaces adhere to well-established standards, enabling the system architectures to support modular designs. To ensure proper design, each of the individual or groups of components could be tested using test interfaces which are accessible through the device pins.
Modularity is also a key aspect of SoC architectures. Typically, the system designer will integrate various functional blocks, including functional blocks that are commonly referred to in the industry as Intellectual Property (IP) cores, IP blocks, or simply IP. For the purposes herein, these functional blocks are referred to as IP blocks or simply “IP”; it will be understood that the terminology IP blocks or IP also covers IP cores and any other component or block generally known as IP, as would be understood by those in the SoC development and manufacturing industries. These IP blocks generally serve one or more dedicated functions and often comprise existing circuit design blocks that are licensed from various vendors or developed in-house. In order to integrate these IP blocks, various interfaces are designed into the SoC. These can be quite challenging, as the well-defined North bridge-South bridge architecture and its standardized interfaces are not practical or desirable for integration in the SoC.
To address this problem, new higher-speed and more modular interfaces have been developed. For example, INTEL Corporation has recently developed new interconnect fabric architectures, including the INTEL On-Chip Scalable Fabric (IOSF). Additionally, other fabric-based interfaces have been developed, including the Open Core Protocol (OCP), and ARM's AMBA (Advanced Microcontroller Bus Architecture) interface. On-chip interconnects such as IOSF interconnect fabrics employ a packetized layered communication protocol and support point-to-point interconnects between IP blocks facilitating easy integration of heterogenous IPs with standard IOSF interfaces.
In order to verify the design integrity of an SoC architecture, testing of the communication between IP blocks and testing of IP functionality and circuitry is required. Under the conventional approach, testing of a given SoC architecture is implemented using Test Access Mechanisms (TAMs) that are devised using ad-hoc techniques. Such TAMs entail dedicated validation and design effort, which needs to be repeated for every lead or derivative SoC. The ad-hoc techniques used also result in extra area and wiring effort at the SoC level, which can cause increased congestion in today's dense SoCs. This can seriously jeopardize Time-To-Market and low-cost goals for SoC. Accordingly, there is a need to facilitate testing of SoC architectures in a manner that is more flexible and predictive.